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The first bootstrap wordline circuit 20 is similar to the driver circuit 20' in Figure 3. The transistors Bootstrap wordline 68 and Q 69 are provided instead of the transistor Q 55 in Figure 3 however, the principle of the operation of the driver circuit 20 is similar to that of the driver circuit 20' set forth above.

In Figure 5, the transistor Q 65 and the capacitor C 66 in Figure 3 are added, and the reset signal supplied to a gate of the transistor Q 64 in Figure 5 may be regarded as a signal having bootstrap wordline same nature as the node N 27 in Figure 3, set forth above. Similarly, the driver circuit 19 has a same circuit construction as that of the driver bootstrap wordline 19' in Figure 3, except that MOS transistors 0 25 and Q 26 are provided instead of the transistor Q 15 in Figure 3. The precharge capacitor C 2 is provided in a same way as the capacitor C 1 in Figure 3, and thus the basic function of the capacitor C 2 is identical to that of the capacitor C 1.

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The bootstrap wordline of the circuit in Figure 5 will be described with reference to Figure 6. When a RAS signal is not supplied to the timing circuit 21, in a reset mode, the timing circuit 21 outputs the reset signal RST having a high level, and the node N 10 is then precharged, as bootstrap wordline forth above. The duration of the reset mode is normally long enough to fully precharge the voltage in the precharge capacitor C 2.

When the voltage VN 4 reaches a predetermined level sufficient to fully turn ON the transistor Q 2 , the voltage VN, o at the node N 10 is output to the output terminal O x. Consequently, the bootstrap wordline V OT at the output terminal O x is superimposed onto the voltage of V cc through the transistor Q ito the voltage from the node N 10 through the transistor Q The bootstrap circuit consisting of the capacitor C 59 and the transistors Q 58 and Q 61has a feature of fully discharging the charge stored in the precharge capacitor C 2 to the output terminal O x through the transistor Q 21 in an operation mode when the clock signal bootstrap wordline enable. The boost capacitor 42, which is connected between nodes 96 and 26, is an inversion capacitor.

During discharging and boosting: When the timing signals on leads and fall to GND, the node 36 goes high, turning device 32 on while turning device 34 off. The nand gate 60 output node 70 stays high until node goes high after the time delay determined by the inverters 62 through This keeps node 72 high, discharging the load to ground through devices 32 and The time delay determines the discharging time of the load and is easily changed by adding an even number of inverters between inverter 68 and gate The discharging of the load through device 32 and device 24 causes the node 26 to bump up.

This in turn bumps the node 96 up because of the capacitive bootstrap wordline through capacitor After the bump in node 26 disappears, the node 96 is fully charged to VDD. After the time delay determined by the bootstrap wordline 62 through 68, node 70 goes low.

This turns device 28 on but bootstrap wordline device 40 off. Device 24 is now in a diode configuration. The low state at node 70 ripples through the inverter chain 78 through 90 and forces node bootstrap wordline to low.


This turns on device 94 at the expense of devices 92 and With device 32 on, the node 30 is boosted to the same voltage as node During resetting: Resetting is accomplished by pulling either the timing signal on lead or to VDD. A large number of storage cells are arranged at the intersections of a matrix of bit bootstrap wordline and word boltstrap. Skip to content Search for:. The gates of transistors 12b and 14b are both coupled to the node 94; hence, the high level signal thereat turns both transistors on.

It will be recalled that transistor 64 has been previously turned on by the high level TTL signal at node Bootstrap Wordline Driver The bootstrap wordline driver shown in Figure is built exclusively from NMOS transistors bootstrap wordline, resulting in the smallest layout. bootstrap wordline array architecture, each wordline in an open digitline architecture connects to . The bootstrap wordline driver shown in Figure is built exclusively.


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